It is often desired in an integrated circuit to delay a signal. In the context of a periodic signal like a clock signal, adjustment of delay can be understood as an adjustment of the phase of the signal. Such phase shifting of a clock signal can be achieved by use of delay lock loops (DLLs) or phase lock loops (PLLs) that are used to generate internal clock signals for an integrated circuit from a master clock signal. Because of the complexity of modern-day integrated circuits, the ability to finely shift the phase of clock signal is particularly important to ensure proper timing within the circuit. For example, DLLs or PLLs are used to set the data output timing in high speed Dynamic Random Access Memories (DRAMs).
A typical analog DLL 10 is shown in FIG. 1. As shown, the DLL 10 derives an output clock signal (ClkOut) from an input clock signal (ClkIn), in which the phase between the two can be tightly controlled. The DLL comprises a variable delay line (VDL) whose delay (tVDL) is controllable given the analog value of a control signal (VDLctrl), and a fixed delay circuit, namely Delay Module (or DM). The output of the delay module (ClkOut_DM) and the ClkIn signals are compared at a phase detector (PD), which essentially determines whether one of the two input signals (ClkIn; ClkOut_DM) are lagging or leading the other, and seeks to bring these two phases into alignment. For example, if ClkOut_DM leads ClkIn, then the phase detector outputs a “down” signal (DN) to reduce the value of VDLctrl, which increases tVDL; if ClkOut_DM lags ClkIn, then the phase detectors outputs an “up” signal (UP) to increase the value of VDLctrl, which decreases tVDL. The bandwidth of the loop is determined in accordance with a loop filter (LF), which in an analog circuit can comprise resistor-capacitor circuits (e.g., an R-C filter). Moreover, and although not shown, the loop filter may comprise a charge pump. In any event, by virtue of the delay module, the output clock signal ClkOut will precedes the input clock signal ClkIn by its delay (tDM). Of course, the DLL circuit 10, may also be digital in nature, with the loop filter being replaced by a digital control, and wherein VDLctrl comprises digital outputs to the VDL (not shown).
In general, and assuming the period of ClkIn is tCK, the loop in DLL circuit 10 establishes a relationship of tVDL+tDM=N*tCK, where N equals the smallest possible integer. Because tVDL is usually not larger than tCK, N is primarily determined by tDM, i.e., the delay through the delay module. Though tDM is a fixed value at given conditions, N is still variable inversely proportional to tCK.
When the delay of the delay module, tDM, is larger than the clock period, tCK, the transfer function of the loop increases in complexity, and instability can result, as will be shown below. Moreover, such problems are worse as the clock frequency increases (i.e., tCK decreases), or as tDM increases. Furthermore, because tDM can vary as a result of process, temperature, or voltage variations, such instability can be particularly hard to control from device to device.
FIGS. 2 and 3 shows Z-domain modeling of analog DLL circuit 10 with (FIG. 2) and without (FIG. 3) a delay module (DM). Kd is the gain for the VDL, and L(z) is the transfer function of charge pump and loop filter. The z−1 block represents the fact that the phase detector compares the current input clock edge with the VDL output derived from the previous input clock edge. In other words, the z−1 block represents one clock cycle delay (tCK). The DM, by contrast, is represented by a z−m block (FIG. 3), meaning that the DM delays by m cycles.
As seen in the figure, the transfer function of FIG. 2 (without the delay module) is a first order system of z, and optimal parameters (Kd, R, C, etc.) for the circuit can be solved with ease. However, the addition of the delay module, as shown in FIG. 3, causes a significant difference. Here, the resulting transfer function is represented by the (m+1)th order of z. It is very difficult to achieve an analytic solution such a high-order system.
As a result, and as alluded to above, a DLL circuit 10 with a relatively high tDM can be unstable, as shown in FIG. 4. As shown, the total delay time of propagation through the loop, tLooP, is about four cycles for an example, and equals the sum of tF and tB, where tF equals the propagation delay though the phase detector (tPD) plus the propagation delay through the loop filter (tLF), and tB=the propagation delay through the VDL (tVDL) plus the propagation delay through the delay module (tDM) (i.e., tF=tPD+tLF; tB=tVDL+tDM). tVDL is generally not larger than tCK, and tF is usually negligible for an analog DLL design, and is shown exaggerated in FIG. 4. (tF may however not be negligible for digital filters). In short, it is largely due to tDM that the delay through the loop can be longer than a single clock cycle.
In FIG. 4, a timing error (tER) between ClkIn and ClkOut_DM is shown. Because initially ClkIn leads ClkOut_DM, UP pulses are needed to try and bring them into alignment. Each UP pulse increases an analog value of the VDL's analog control signal, VDLctrl, which decreases tVDL; each down pulse (DN) achieves the opposite effect. (Fixed pulse widths for UP and DN are assumed for simplicity of explanation).
However, notice that it takes significant time (i.e., tLooP) for the output of the phase detector (UP; DN) to take effect through the loop so as to update the phase at the input of the phase detector. In the mean time, before this change in phase is effected, the phase detector continues to generate the same signals (initially, UP in FIG. 4) and does so at every clock period, regardless of whether they are needed or not, and despite that the fact that any phase shift wrought by earlier signals is not yet known. Thus, in the example of FIG. 4, four UP pulses are output before any change in phase (tER) is registered. This discrepancy in frequency between the clock frequency (1/tCK) and the loop frequency (1/tLooP) causes the loop to overreact and become unstable. Specifically, the timing error, tER, does not converge but oscillates. The amplitude and period of the oscillation depends on the loop gain and the loop delay (tLooP).
The conventional solution to this problem involved decreasing the loop's gain and/or reducing the loop's bandwidth. This can be accomplished by increasing loop filter's resistance-capacitance values (assuming an analog circuit), reducing the charge pumping current, or increasing the size of the loop filter. But these solutions can consumes larger layout areas and can considerably decreases the tracking bandwidth (i.e., loop gain divided by loop delay), resulting in a longer time to achieve a phase “lock.” In short, such previous approaches involved undesirable trade offs between maximum frequency performance, stability, tracking bandwidth, and layout area. A better solution is therefore needed.